ALTERA TERASIC USB BLASTER DRIVER DOWNLOAD

For the cheap clone, the spacing is huge: This is the first transaction that travels over the JTAG cable when you issue the “nios2-terminal” command. It looks like the cheap clone is able to squeeze out bits really fast, but there’s quite a bit of software overhead in processing the next byte in the USB packet. And at the end you have a suffix with 2 slow clock cycles. And here’s the equivalent of the cheap clone. We have a prefix with 8 slow clocks, but in between the second and the third slow clock, there’s a signal fast clock group.

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We have a prefix with 8 slow clocks, but in between terxsic second and the third slow clock, there’s a signal fast clock group. In the middle we have the expected 16 fast clock groups. For this investigation, it doesn’t matter what gets transported when, but it’s almost certain that the slow clock cycles are used to move the JTAG TAP from iDLE state to the scan DR or scan IR state, and that the fast clock groups are used to rapidly scan data in and out of a scan data register.

It’s not that it’s broken: All processing balster done with a simply state machine. As I wrote earlierthe biggest issue with the cheap clone is that it doesn’t work on my eeColor Color3 board. A fast clock group sets the clock at 12MHz instead of 6MHz. And here’s the equivalent of the cheap clone.

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If we ignore for a second that the cheap clone doesn’t work on this particular board, the biggest consequence of the chapeau clone is that bulk transfers are much slower: Zooming in on the slow clocks, we see a clock frequency of kHz.

For the cheap clone, the spacing is huge: What remains is the question about why the cheap clone doesn’t work. I was supposed to work on getting the SiI up and runningbut UPS delivered a nice package today:. While the Terasic was rock solid in its communication with the Color3 board.

Sign up Already a member? In addition, there are roughly 3 idle cycles between a fast clock group. There are 3 major sections: My money is on the clock speed: This is the first transaction that travels over the JTAG cable when you issue the “nios2-terminal” command. The Terasic doesn’t have that problem: About Us Contact Hackaday.

We see a similar pattern, but interestingly enough, it’s not the same. A really interesting difference is in the spacing between fast clock groups: It looks like the cheap clone is able to squeeze out bits really fast, but there’s quite a bit of software overhead in processing the next byte in the USB packet.

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The suffix is really different, with 6 clock clocks but also a fast clock group in between. It may be that 12MHz is really just pushing things too much.

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Yes, delete it Cancel. The most important signal here is TCK, in yellow. The cheap clone was never able to get reliable contact. But the cheap clone runs TCK at exactly double the speed of the Terasic, and both devices only use a flimsy, cheap flat cable.

When you zoom in on the slow clock cycles, you can measure a TCK frequency of kHz: The set of signals below usn is a slightly zoomed in version of the one above. For the overview, look at the upper set. Meanwhile, during a fast clock group, the clock toggles at 6MHz.

Terasic USB Blaster Cable For Altera – % compatible with Altera USB blaster download cable

In the middle there are 16 groups with fast clock cycles each group is itself 8 clock cycles. And at the end you have a suffix with 2 slow clock cycles.

I was supposed to work on getting the SiI up and runningbut UPS delivered a nice package today: